In the field of radio communications systems, there has been a continuing goal to design a simple low-cost frequency synthesizer that can provide a large library of discrete frequencies over a very wide frequency spectrum. Direct digital frequency synthesis is a digital technique of frequency synthesis that is often used in phase modulation, frequency modulation and frequency hopping schemes in spread spectrum communications. This technique is advantageous because of the high speed at which the output frequency can be changed, the small frequency step size that it makes available, and the ability to digitally control the phase or frequency. A circuit arrangement using this technique is referred to as a Direct Digital Synthesizer or "DDS".
The output frequency of a DDS is represented as a digital output and is determined by an input digital frequency control word, which can be generated by a logic device such as a digital processor or computer. Many modulation schemes can be implemented with a DDS. These schemes include, among others, FSK (frequency shift keying), FM (frequency modulation), and PM (phase modulation). Thus, the output frequency of a DDS can be frequency modulated according to the information digitized by the logic device, for example, using FSK modulation. In addition to the FSK modulation, the window of modulated frequencies can hop, thereby moving the window of modulated frequencies in a coded scheme to avoid jamming or decoding by unauthorized transceivers. The agility and the frequency resolution of the DDS makes it superior to other types of synthesizers in such an application and gives an unauthorized transceiver less time to lock onto the correct frequency. Naturally, the authorized receiver must hop to the correct frequency to receive the modulated information. A logic device in the receiver generates the correct digital control word for the receiver's DDS and subsequent down-conversion, demodulation, and decoding.
Typically, a DDS includes a digital accumulator, which is configured as a digital integrator, using a latch and full adder with the output sum at each accumulator stage and the input digital frequency control word as inputs to the adder. The frequency word determines the step size by which the accumulated sum is incremented. Each step represents a step or increment in phase and in corresponding frequency.
In an accumulator having "N" carryover summing stages, for instance, the clock frequency into the DDS is 2.sup.Nth times the frequency difference represented by each step or increment in phase. Thus, all the frequencies are not sub-multiples of the clock frequency, and an accumulator overflow occurs with varying remainders left in the accumulator corresponding to the difference between the clock frequency and the closest multiple of the step.
Present DDS circuits require a clock frequency that is 2.sup.N times the frequency increment, such as: EQU 2.sup.20 .times.10Hertz=10.48576 Hertz,
where N is 20 and 10 Hertz is the frequency increment to obtain a clock frequency of 10.48576 Hertz. It is difficult to obtain such a convenient clock frequency without requiring specialized circuits which are slow in getting initialized.
Accordingly, there is a need for a DDS with a conveniently adjustable clock frequency.